The invention discloses a flash memory and low speed read mode control circuit. The flash memory and low speed read mode control circuit comprises a charge pump, a first divider circuit formed through serial connection of two resistors and a first switch, and a second divider circuit formed through serial connection of two capacitors. The first switch is used for switching the data reading mode and the charge pump electric leakage mode of the above low speed read mode, and in the data reading mode, a first voltage division formed by the two resistors is fed back to the input end of the charge pump through a comparator, an NAND gate and a buffer to make the stable value of the voltage proportional to the first voltage division. In the charge pump electric leakage mode, the second divider circuit monitors the output voltage of the charge pump, a feedback signal is formed and is sent to the input end of the charge pump to start the charge pump when the output voltage is lower than a low threshold voltage, and a feedback signal is formed and is sent to the input end of the charge pump to stop the charge pump when the output voltage is higher than the low threshold voltage. The flash memory and low speed read mode control circuit greatly reduces the average current of the whole low speed read mode and reduces the power consumption of the reading process.