A CSP structure of a power device disclosed by the present invention is characterized in that by utilizing the scribing ways between the chips and/or the areas at the four corners of a chip and by using a corrosion or scribing method, the epitaxial layers at the areas are removed to expose an N+ substrate, and then a layer of metal is evaporated and plated on the surface of the chip by a sputtering or evaporation method to lead an N+ layer to the surface, thereby realizing the CSP requirements. The beneficial effects of the present invention are that the surface area of the chip is utilized effectively and fully, and the on-resistance of the power device is reduced greatest possibly.