A controller (215) integrated in a memory physical layer interface (PHY) (140, 205) can be used to control training used to configure the memory PHY for communication with an associated external memory (135) such as a dynamic random access memory (DRAM), thereby removing the need to provide training sequences over a data pipeline between a BIOS (120) and the memory PHY. For example, a controller (215) integrated in the memory PHY can control read training and write training of the memory PHY for communication with the external memory based on a training algorithm. The training algorithm may be a seedless training algorithm that converges on a solution for a timing delay and a voltage offset between the memory PHY and the external memory without receiving, from the BIOS, seed information that characterizes a signal path traversed by training sequences or commands generated by the training algorithm.