The present invention relates to a system and method for controlling power consumption in a digital phase locked loop (DPLL). An apparatus includes a programmable frequency device adapted to generate a reference clock selected from a group of distinct frequency clocks, wherein the programmable frequency device is further adapted to switch between the different frequency clocks while maintaining the same temporal relationship of the trigger edge of said reference clock. The device further comprises a phase-locked loop (PLL), such as a digital phase-locked loop (DPLL), which uses the selected reference clock to establish a predetermined phase relationship between the input signal and the output signal. Maintaining a substantially identical temporal relationship of said reference clock by switching between different frequency clocks does not significantly interfere with the continuous and efficient operation of said phase locked loop (PLL) while altering said reference clock. The system and method can be used to control the power consumption of the device.