The invention discloses a method for improving a linearity of a pipelined successive-approximation analog-to-digital converter. The method is applied to a high-performance analog-to-digital converter in the field of microelectronics and solid-state electronics. The method is characterized in that an ADC sampling rate does not need to be sacrificed; an additional operational amplifier does not need to be introduced to carry out noise shaping; an auxiliary DAC or a slow and accurate ADC does not need to be introduced; a Dither also does not need to be introduced; only capacitors of a first-stage capacitor array of the pipelined successive-approximation analog-to-digital converter need to be grouped; and different capacitor combinations are adopted for each conversion, so that accumulation of errors of capacitor mismatch at the same codon can be avoided. Therefore, compared with a conventional DAC foreground correction method, LMS correction algorithm or correction method for improving a linearity by slow and accurate auxiliary ADC correction, the method disclosed by the invention has effects of no sacrifice of the sampling rate, simpler structure, smaller occupied area of a chip and higher easiness for implementing on a chip.