The invention relates to the field of communication and in particular to an interrupt signal processing system. According to the system disclosed by the invention, an interrupt processing module function is increased on CPLD between a master control board and an interface board, and the operation of interrupt state and control register between the master control board and the interface board is realized by utilizing two serial signal lines. All interrupt states of the interface board are reported to the CPLD of the master control board in a serial bus manner, the master control board processor only needs to execute once and perform bus access when interrupt happens, and the interrupt state is acquired from the CPLD of the master control board. Therefore, instruction per cycle allowing the processor to access peripherals is greatly reduced, load of the processor is reduced, and the interrupt response time is accelerated. The interrupt needs to be transferred between the interface board and the master control board by two signal lines only, and signal pins are greatly saved.