The present invention relates to a Virtex-based FPGA (programmable logic device) chip line pair fault test method. The method includes the following steps that: line pairs at adjacent rows or adjacent columns are connected together through configuration logical units, and the input of IO (input/output) blocks is connected with the input of the line pairs through the initial configuration logic units, and the output of the IO blocks is connected with the output of the line pairs through the terminal configuration logic units; and line pairs in the east (E2BEG) and line pairs in the west (W2BEG) are connected together end to end through the configuration logic units, or line pairs in the south (S2BEG) and line pairs in the north (N2BEG) are connected together end to end through the configuration logic units. According to the method of the invention, line pair fault testing can be carried out by one-time configuration, and therefore, testing efficiency and a fault coverage rate can be improved; and based on multiple times of configuration, a malfunctioned line pair in a certain line or a certain column can be located.