The invention relates to a global layout method for a chip. The global layout method for the chip comprises the steps of: creating multiple density boxes according to the structure of the chip, and acquiring a net list; performing initial layout for the chip according to a layout algorithm, mapping multiple instances to the corresponding density boxes respectively, and then judging whether the layout of the chip satisfies a global layout ending condition; if not satisfying, acquiring a set density of multiple box sets on the chip; taking the box sets having set densities greater than a density factor as seed box sets, sequentially expanding the seed box sets according to the set densities from high to low, till the set densities of the seed box sets are smaller than the density factor; judging whether the layout of the chip satisfies the global layout ending condition, and when the layout of the chip satisfies the global layout ending condition, ending the layout. The method greatly reduces the number of iterations of global layout of the chip, and distributes the instances more uniformly while reducing the global layout time.