Provided is a method for manufacturing an array substrate. The method comprises: (S110) forming a thin film transistor and a peripheral circuit; (S120) forming a passivation layer (8) covering at least the thin film transistor and the peripheral circuit; (S130) forming a first via hole (9) penetrating the passivation layer and exposing a drain electrode (6) of a part of the thin film transistor, and a second via hole (10) penetrating the passivation layer and exposing a part of the peripheral circuit; (S140) forming on the passivation layer a pattern (11) comprising a first conductive layer, the first conductive layer covering the first via hole and the second via hole; and (S150) forming on the first conductive layer a pattern (12) comprising a reflective metal layer and a pattern (13) comprising a second conductive layer, the second conductive layer covering the second via hole.