The invention discloses an interleaved parallel circuit, a power integrated module and a power integrated chip, which belong to the technical field of power electronics. The interleaved parallel circuit includes a first bridge arm and a second bridge arm. The first bridge arm includes a first upper bridge arm switch and a first lower bridge arm switch. The second bridge arm includes a second upperbridge arm switch and a second lower bridge arm switch. The first bridge arm and the second bridge arm are at least partially formed on a wafer which includes multiple first cell groups and multiplesecond cell groups. The multiple first cell groups are used for forming the first upper bridge arm switch, and the multiple second cell groups are used for forming the second upper bridge arm switch,or, the multiple first cell groups are used for forming the first lower bridge arm switch, and the multiple second cell groups are used for forming the second lower bridge arm switch. The multiple first cell groups and the multiple second cell groups are opened or closed in a staggered manner. The path loss for the conduction of each level of a chip can be reduced, and the overall efficiency of apower system can be improved.