The invention provides a multi-phase parallel DCDC circuit and a chip structure thereof, which are used for reducing output parasitic of a loop operational amplifier EA unit and a COMP, thereby improving the loop bandwidth and accelerating the transient response. The multi-phase parallel DCDC circuit provided by the embodiment of the invention comprises a loop operational amplifier EA unit, N output stage circuit units and M driving units, wherein one driving unit is corresponding to at least one output stage circuit unit, and each output stage circuit unit comprises a COMP and a power stage circuit, wherein N is an integer larger than or equal to 2, and M is an integer smaller than or equal to N; the output end of the loop operational amplifier EA unit is connected with the input ends ofthe driving units; the output ends of the driving units are connected with the input end of the COMP in the corresponding output stage circuit unit, and the output ends of the COMPs is are with the input end of the power stage circuit in the same output stage circuit unit; and the input end of the loop operational amplifier EA unit is connected with the output ends of all power stage circuits.