The invention discloses a switched capacitor integrator offset voltage elimination circuit and an elimination method thereof. The circuit comprises a first capacitor C1, a second capacitor C2, a thirdcapacitor Cload, a fourth capacitor Cf, a first switch S1, a second switch S2, a third switch RST _ PGA, a fourth switch S1d, a reference voltage Vref _ PGA, a VOS offset voltage source and an integrator. The first end of the first capacitor C1 is connected with an input signal, and the second end of the first capacitor C1 is connected with the second end of the second capacitor C2, the first endof the third capacitor Cload, the first end of the fourth capacitor Cf, the first end of the second switch S2, the first end of the third switch RST _ PGA and the first end of the VOS offset voltagesource. According to the technical scheme, the influence of a mismatched switched capacitor integrator is eliminated by optimizing a switch structure and a related double-sampling technology. The circuit is easy to implement, low in power consumption, capable of being used in a single-ended circuit and a differential circuit and wide in application range.