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Invention Publication
CN110120810A 一种同步计数器 有权

一种同步计数器
Abstract:
本发明公开了一种同步计数器，包括输入端COUNTER ENABLE、输入端CLOCK、输出端CARRY、输出端CARRY_B、状态输出端Q0、状态输出端Q1、状态输出端Q2和状态输出端Q3、触发器DFF1、触发器DFF2、触发器DFF3、触发器DFF4、触发器DFF5、二输入与非门ND1、二输入或非门NR1、二输入与非门ND2、二输入或非门NR2、二输入与非门ND3、二输入或非门NR3和非门INV1，其中，触发器DFF1、触发器DFF2、触发器DFF4的输入端和输出端分别包括输入端EN1和输入端T1以及输出端Q1和输出端QN1，触发器DFF3和触发器DFF5的输入端和输出端分别包括输入端ENB和输入端T2以及输出端Q2和输出端QN2，输入端COUNTER ENABLE分别与触发器DFF1的输入端EN1、二输入与非门ND1的输入端以及触发器DFF2的输入端EN1连接。
Abstract(English):

The invention discloses a synchronous counter. The synchronous counter comprises an input end COUNTER ENABLE, an input end, CLOCK, an output end CARRY, an output end CARRY_B, a state output end Q0, astate output end Q1, a state output end Q2 and a state output end Q3, a trigger DFF1, a trigger DFF2, a trigger DFF3, a trigger DFF4, a trigger DFF5, a two-input NAND gate ND1, a two-input NOR gate NR1, a two-input NAND gate ND2, a two-input NOR gate NR2, a two-input NAND gate ND3, a two-input NOR gate NR3 and a NOR gate INV1, wherein the input ends and the output ends of the trigger DFF1, the trigger DFF2 and the trigger DFF4 respectively comprise an input end EN1, an input end T1, an output end Q1 and an output end QN1; the input ends and the output ends of the trigger DFF3 and the trigger DFF5 respectively comprise an input end ENB, an input end T2, an output end Q2 and an output end QN2; the input end COUNTER ENABLE is connected with the input end EN1 of the trigger DFF1, the input endof the two-input NAND gate ND1 and the input end EN1 of the trigger DFF2.

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