The utility model discloses an access memory request dispatching device, which comprises a plurality of Bank access memory request register files, a plurality of Bank dispatchers and a plurality of DRAM dispatcher. The access memory request dispatching device is characterized by further comprising a plurality of window restraining circuits which include an access memory request counter and a window length register. The window restraining circuits which are arranged in access memory request dispatching circuit can guarantee the Bank dispatcher to only dispatch access memory request with limited quantity at a time, thereby being capable of preventing access memory requests with relatively poor locality of an individual address to be unlimitedly delayed to dispatch by the Bank dispatchers, eliminating threading starvation caused by out-of-order dispatching of the access memory requests, and increasing the lowest treatment capacity of a multi-core processor.