A negative overvoltage protection circuit for an insulated vertical PNP transistor (QP) the emitter whereof defines the input (VIN), the collector whereof defines the output (VOUT) and the base whereof is connected to an NPN driving transistor (QN). In order to maximally extend the negative overvoltage which can be applied to the output, the protection circuit comprises an output voltage sensor (R4), a voltage reference (VB), a comparator (Q2,Q3,D1) which is connected in input to the voltage reference (VB) and to the sensor (R4) and generates in output an activation signal when the output voltage of the PNP transistor (QP) becomes smaller than the reference, a switch (Q5) which is controlled by the comparator (Q2,Q3,D1) to switch off the NPN driving transistor (QP) upon the reception of the activation signal and a low-impedance circuit (Q4) which is connected between the emitter and the base of the insulated vertical PNP transistor (QP) and is activated by the activation signal, in a manner suitable for bringing the insulated vertical PNP transistor (QP) practically to BVCBO.