Invention Patent
IT8025969D0
未知
- Patent Title:
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Application No.: IT2596980Application Date: 1980-11-14
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Publication No.: IT8025969D0Publication Date: 1980-11-14
- Inventor: SCHLIG EUGENE STEWART
- Applicant: IBM
- Assignee: IBM
- Current Assignee: IBM
- Priority: US10139079 1979-12-07
- Main IPC: G11C8/16
- IPC: G11C8/16 ; G11C11/411 ; G11C
Abstract:
A multiple access store having bipolar monolithic memory cells. Each cell includes a memory flip-flop comprised of cross-connected NPN transistors. A single concurrent read and write for each cell is achieved by a pair of accessing transistors, one accessing transistor of the pair connected at its base to the base of one of the flip-flop transistors and the other accessing transistor of the pair connected at its base to the base of the other of the flip-flop transistors. Each accessing transistor of an accessing transistor pair is connected at its collector to an associated bit/sense line. The emitter of each of the accessing transistors of an accessing transistor pair are connected together and the connected emitters are connected to a device that supplies a current supply to the emitters in response to a word signal. The emitters of the cross-connected flip-flop transistors are connected to an associated mode select line over which is applied a signal having a potential defining a write mode condition and a signal having a lower potential defining a read mode condition for the cell. Each pair of bit/sense lines and associated pair of accessing transistors that is added to each of the cells of a memory array may be operated to add an additional concurrent write of one word and a read of a different word for the array.
Public/Granted literature
- IT1149263B Public/Granted day:1986-12-03
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