Invention Grant
- Patent Title: Uniform load processing for parallel thread sub-sets
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Application No.: US13412438Application Date: 2012-03-05
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Publication No.: US10007527B2Publication Date: 2018-06-26
- Inventor: Michael Fetterman , Stewart Glenn Carlton , Douglas J. Hahn , Rajeshwaran Selvanesan , Shirish Gadre , Steven James Heinrich
- Applicant: Michael Fetterman , Stewart Glenn Carlton , Douglas J. Hahn , Rajeshwaran Selvanesan , Shirish Gadre , Steven James Heinrich
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA CORPORATION
- Current Assignee: NVIDIA CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Artegis Law Group, LLP
- Main IPC: G06F15/00
- IPC: G06F15/00 ; G06F7/38 ; G06F9/00 ; G06F9/44 ; G06F9/38

Abstract:
One embodiment of the present invention sets forth a technique for processing load instructions for parallel threads of a thread group when a sub-set of the parallel threads request the same memory address. The load/store unit determines if the memory addresses for each sub-set of parallel threads match based on one or more uniform patterns. When a match is achieved for at least one of the uniform patterns, the load/store unit transmits a read request to retrieve data for the sub-set of parallel threads. The number of read requests transmitted is reduced compared with performing a separate read request for each thread in the sub-set. A variety of uniform patterns may be defined based on common access patterns present in program instructions. A variety of uniform patterns may also be defined based on interconnect constraints between the load/store unit and the memory when a full crossbar interconnect is not available.
Public/Granted literature
- US20130232322A1 UNIFORM LOAD PROCESSING FOR PARALLEL THREAD SUB-SETS Public/Granted day:2013-09-05
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