A method and apparatus for generating an address sequence in a memory device is provided. The method includes providing a memory array having a set of unique addresses, storing one of a first subset of the set of unique addresses in a first storage element, storing one of a second subset of the set of unique addresses in a second storage element, and generating a sequence of addresses to test the memory array. The sequence of addresses are formed by alternately outputting addresses stored in the first storage element and the second storage element such that the sequence of addresses causes each unique address of the set to transition only once. The sequence of addresses can be used to efficiently test the memory array during a built-in self-test (BIST).