Invention Grant
- Patent Title: Low profile leaded semiconductor package and method of fabricating the same
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Application No.: US15784706Application Date: 2017-10-16
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Publication No.: US10008438B2Publication Date: 2018-06-26
- Inventor: Richard K Williams
- Applicant: Richard K Williams
- Applicant Address: LU Luxembourg
- Assignee: Adventive IPBank
- Current Assignee: Adventive IPBank
- Current Assignee Address: LU Luxembourg
- Agency: Patentability Associates
- Agent David E. Steuber
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H05K5/02 ; H05K7/18 ; H01L23/498 ; H01L21/48 ; H01L23/00

Abstract:
In a semiconductor package a lead having a bottom surface coplanar with the flat bottom surface of the plastic body extends outward at the bottom of the vertical side surface of the plastic body. The result is a package with a minimal footprint that is suitable for the technique known as “wave soldering” that is used in relatively low-cost printed circuit board assembly factories. Methods of fabricating the package are disclosed, in particular a method of fabricating a package including an exposed die pad.
Public/Granted literature
- US20180040545A1 Method Of Fabricating Low Profile Leaded Semiconductor Package Public/Granted day:2018-02-08
Information query
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