A memory system includes a core power supply node configured to provide a core power supply; backup regulator configured to provide a backup power supply; memory configured to be powered by the core power supply or the backup power supply; threshold detection circuitry configured to provide a first indicator that when asserted indicates the core power supply has fallen to a first threshold, a second indicator that when asserted indicates the core power supply has fallen to a second threshold, and a third indicator that when asserted indicates the core power supply has fallen to a third threshold. The memory system also includes power sequence detection circuitry is configured to determine, upon the core power supply falling and based on which of the first, second, and third indicators are asserted, whether the asserted indicators have been asserted in a correct sequence and provide a first test result accordingly.