Methods and apparatuses for parallel processing data are disclosed. One method includes reading items of data from a memory using at least memory access address, confirming items of data with the same memory address among the read items of data, and masking the confirmed items of data other than one of the confirmed items of data. A correction value is generated for the memory access address using the confirmed items of data, and an operation is performed on data that has not been masked using the confirmed items of data and the correction value. Data obtained by operating on the data that has not been masked is stored as at least on representative data item for the data items with the same memory address. A schedule of a compiler of a processor is adjusted by performing bypassing of memory access address alias checking for at least one memory access address.