Invention Grant
- Patent Title: Maximizing parallel processing in graphics processors
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Application No.: US13174116Application Date: 2011-06-30
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Publication No.: US10013731B2Publication Date: 2018-07-03
- Inventor: Selvakumar Panneer , Carl S. Marshall
- Applicant: Selvakumar Panneer , Carl S. Marshall
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Jordan IP Law, LLC
- Main IPC: G06T1/20
- IPC: G06T1/20

Abstract:
Methods and systems may include a computing system having a graphics processor with a three-dimensional (3D) pipeline, one or more processing units, and compute kernel logic to process two-dimensional (2D) command. A graphics processing unit (GPU) scheduler may dispatch the 2D command directly to the one or more processing units. In one example, the 2D command includes at least one of a render target clear command, a depth-stencil clear command, a resource resolving command and a resource copy command.
Public/Granted literature
- US20130002689A1 MAXIMIZING PARALLEL PROCESSING IN GRAPHICS PROCESSORS Public/Granted day:2013-01-03
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