Invention Grant
- Patent Title: Method for wafer dicing
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Application No.: US15654512Application Date: 2017-07-19
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Publication No.: US10014269B2Publication Date: 2018-07-03
- Inventor: Yueh-Chuan Lee , Chia-Chan Chen
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/00 ; H01L23/58 ; H01L21/78 ; H01L21/306 ; H01L33/00

Abstract:
The semiconductor die includes a base body, protruding portions and bonding pads. The base body has sidewalls. The protruding portions are laterally protruding from the sidewalls respectively. The bonding pads are disposed on the protruding portions respectively. The wafer dicing method includes following operations. Chips are formed on a semiconductor wafer. Bonding pads are formed at a border line between every two of the adjacent chips. A scribe line is formed and disposed along the bonding pads. A photolithographic pattern is formed on a top layer of the semiconductor wafer to expose the scribe line. The scribe line is etched to a depth in the semiconductor wafer substantially below the top layer to form an etched pattern. A back surface of the semiconductor wafer is thinned until the etched pattern in the semiconductor wafer is exposed.
Public/Granted literature
- US20170317043A1 METHOD FOR WAFER DICING Public/Granted day:2017-11-02
Information query
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