Invention Grant
- Patent Title: Array substrate comprising a power wire layer and manufacturing method thereof
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Application No.: US14443798Application Date: 2014-09-04
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Publication No.: US10014360B2Publication Date: 2018-07-03
- Inventor: Cuili Gai , Zhongyuan Wu
- Applicant: BOE TECHNOLOGY GROUP CO., LTD.
- Applicant Address: CN Beijing
- Assignee: BOE TECHNOLOGY GROUP CO., LTD.
- Current Assignee: BOE TECHNOLOGY GROUP CO., LTD.
- Current Assignee Address: CN Beijing
- Agency: Nath, Goldberg & Meyer
- Agent Joshua B. Goldberg
- Priority: CN201410266064 20140613
- International Application: PCT/CN2014/085926 WO 20140904
- International Announcement: WO2015/188472 WO 20151217
- Main IPC: H01L27/32
- IPC: H01L27/32 ; H01L21/76 ; H01L21/77 ; H01L23/52 ; H01L29/00 ; H01L27/12 ; H01L29/66 ; H01L29/78 ; G02F1/13

Abstract:
The present invention provides an array substrate and a manufacturing method thereof. The array substrate of the present invention comprises multiple pixel units arranged in an array, each pixel unit comprising a substrate, an active layer, a source layer and a drain layer arranged in the same layer, and a gate layer; wherein each pixel unit further comprises a power wire layer connected to the source layer via a via hole. Since the power wire layer of the present invention is separately provided as a layer, the area of the projection of the power wire layer on the substrate may be larger, that is, the conductive cross-sectional area of the power wire layer may be larger, and thus the resistance of the power wire layer is decreased. Therefore, difference among currents of different pixel units is reduced, and thus the mura phenomenon generated in displaying is alleviated.
Public/Granted literature
- US20160247874A1 ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF Public/Granted day:2016-08-25
Information query
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