Invention Grant
- Patent Title: Stressed nanowire stack for field effect transistor
-
Application No.: US15064090Application Date: 2016-03-08
-
Publication No.: US10014371B2Publication Date: 2018-07-03
- Inventor: Martin M. Frank , Pouya Hashemi , Ali Khakifirooz , Alexander Reznicek
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Louis J. Percello, Esq.
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/423 ; H01L29/78 ; H01L27/12 ; H01L29/49 ; H01L29/66 ; H01L21/84 ; H01L21/3213 ; H01L21/311 ; B82Y10/00 ; H01L29/40 ; H01L29/775 ; H01L29/417 ; H01L29/786

Abstract:
A disposable gate structure is formed over the alternating stack of first semiconductor material portions and second semiconductor material portions. The second semiconductor material portions are removed selective to the first semiconductor material portions to form suspended semiconductor nanowires. Isolated gate structures are formed in regions underlying the disposable gate structure by deposition and recessing of a first gate dielectric layer and a first gate conductor layer. After formation of a gate spacer, source regions, and drain regions, raised source and drain regions are formed on the source regions and the drain regions by selective deposition of a semiconductor material. The disposable gate structure is replaced with a replacement gate structure by deposition and patterning of a second gate dielectric layer and a second gate conductor layer. Distortion of the suspended semiconductor nanowires is prevented by the disposable gate structure and the isolated gate structures.
Public/Granted literature
- US20160190246A1 STRESSED NANOWIRE STACK FOR FIELD EFFECT TRANSISTOR Public/Granted day:2016-06-30
Information query
IPC分类: