Invention Grant
- Patent Title: Bipolar junction transistors with a combined vertical-lateral architecture
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Application No.: US15383171Application Date: 2016-12-19
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Publication No.: US10014397B1Publication Date: 2018-07-03
- Inventor: Vibhor Jain , Qizhi Liu , David L. Harame , Renata Camillo-Castillo
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Thompson Hine LLP
- Agent Anthony Canale
- Main IPC: H01L29/737
- IPC: H01L29/737 ; H01L29/06 ; H01L29/66 ; H01L29/165 ; H01L29/417 ; H01L21/265 ; H01L29/735 ; H01L27/12

Abstract:
Device structures and fabrication methods for a bipolar junction transistor. The device structure includes an intrinsic base, an emitter having a vertical arrangement relative to the intrinsic base, and a collector having a lateral arrangement relative to the intrinsic base. The device structure may be fabricated by forming the intrinsic base and the collector in a semiconductor layer, and epitaxially growing the emitter on the intrinsic base and with a vertical arrangement relative to the intrinsic base. The collector and the intrinsic base have a lateral arrangement within the semiconductor layer.
Public/Granted literature
- US20180175180A1 BIPOLAR JUNCTION TRANSISTORS WITH A COMBINED VERTICAL-LATERAL ARCHITECTURE Public/Granted day:2018-06-21
Information query
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