Address bit remapping scheme to reduce access granularity of DRAM accesses
Abstract:
One embodiment of the present invention sets forth a method for accessing non-contiguous locations within a DRAM memory page by sending a first column address command to a first DRAM device using a first subset of pins and sending a second column address command to a second DRAM device using a second subset of repurposed pins. The technique requires minimal additional pins, space, and power consumption. Further, sending multiple column address commands allows for increased granularity of DRAM accesses and therefore more efficient use of pins. The technique for accessing non-contiguous locations within a DRAM memory page.
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