- Patent Title: Semiconductor device and semiconductor device manufacturing method
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Application No.: US15107313Application Date: 2014-08-04
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Publication No.: US10020390B2Publication Date: 2018-07-10
- Inventor: Jun Saito , Hirokazu Fujiwara , Tomoharu Ikeda , Yukihiko Watanabe , Toshimasa Yamamoto
- Applicant: Jun Saito , Hirokazu Fujiwara , Tomoharu Ikeda , Yukihiko Watanabe , Toshimasa Yamamoto
- Applicant Address: JP Toyota JP Kariya
- Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA,DENSO CORPORATION
- Current Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA,DENSO CORPORATION
- Current Assignee Address: JP Toyota JP Kariya
- Agency: Oliff PLC
- Priority: JP2013-269265 20131226
- International Application: PCT/JP2014/070521 WO 20140804
- International Announcement: WO2015/098168 WO 20150702
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/06 ; H01L29/10 ; H01L29/40 ; H01L29/16 ; H01L29/66 ; H01L21/04 ; H01L21/265
Abstract:
A technique achieving a higher voltage resistance by a depletion layer extending quickly within a circumferential region is provided. A semiconductor device includes an element region in which an insulated gate type switching element is provided and a circumferential region adjacent to the element region. First and second trenches are provided in the circumferential region. A front surface region of the second-conductivity-type is provided between the first and second trenches. First and second bottom surface regions of the second-conductivity-type are provided in bottom surface ranges of the first and second trenches. First and second side surface regions of the second-conductivity-type connecting the front surface region and the first or second bottom surface region is provided along side surfaces of the first and second trenches. Low area density regions are provided in at least parts of the first and second side surface regions.
Public/Granted literature
- US20170012121A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD Public/Granted day:2017-01-12
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