Invention Grant
- Patent Title: Semiconductor device having compressively strained channel region and method of making same
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Application No.: US14188835Application Date: 2014-02-25
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Publication No.: US10020399B2Publication Date: 2018-07-10
- Inventor: Toshiharu Nagumo
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Young & Thompson
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L29/10

Abstract:
A semiconductor device and method making it utilize a three-dimensional channel region comprising a core of a first semiconductor material and an epitaxial covering of a second semiconductor material. The first and second semiconductor materials have respectively different lattice constants, thereby to create a strain in the epitaxial covering. The devices are formed by a gate-last process, so that the second semiconductor material is deposited only after the high temperature processes have been performed. Consequently, the lattice strain is not substantially relaxed, and the improved performance benefits of the lattice strained channel region are not compromised.
Public/Granted literature
- US10069010B2 Semiconductor device having compressively strained channel region and method of making same Public/Granted day:2018-09-04
Information query
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