Invention Grant
- Patent Title: Methods for straining a transistor gate through interlayer dielectric (ILD) doping schemes
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Application No.: US15399241Application Date: 2017-01-05
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Publication No.: US10020401B2Publication Date: 2018-07-10
- Inventor: Cheng-Ta Wu , Chii-Ming Wu , Shiu-Ko Jangjian , Kun-Tzu Lin , Lan-Fang Chang
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Hauptman Ham, LLP
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L21/3115 ; H01L21/8234 ; H01L29/51 ; H01L29/78 ; H01L29/423 ; H01L29/40 ; H01L29/49 ; H01L29/41
Abstract:
A method of making a semiconductor device includes doping a first portion of an interlayer dielectric (ILD) with an oxygen-containing material, wherein the ILD is over a substrate. The method further includes doping a second portion of the ILD with a large species material. The second portion includes an area of the ILD below the first portion, and the second portion is separated from the substrate. The method further includes annealing the ILD.
Public/Granted literature
- US20180151740A1 Methods for Straining a Transistor Gate through Interlayer Dielectric (ILD) Doping Schemes Public/Granted day:2018-05-31
Information query
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