A semiconductor device may include an inversion control signal generation circuit, a pattern control signal generation circuit, and a data input/output (I/O) circuit. The inversion control signal generation circuit may generate an inversion control signal according to a logic level combination of bit patterns included in at least one of a first address and a second address. The pattern control signal generation circuit may generate a pattern control signal from a pre-control signal in response to the inversion control signal. In response to the pattern control signal, the data input/output (I/O) circuit may generate data signals that will be output to an internal I/O line based on data signals loaded on a local I/O line.