- Patent Title: Array substrate and fabrication method thereof, and display device
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Application No.: US15110230Application Date: 2015-11-13
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Publication No.: US10025143B2Publication Date: 2018-07-17
- Inventor: Xiaofei Yang , Yuqing Yang , Yanxia Xin , Zailong Mo , Xue Jiang , Xun Mou
- Applicant: BOE TECHNOLOGY GROUP CO., LTD. , CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
- Applicant Address: CN Beijing CN Chengdu, Sichuan
- Assignee: BOE TECHNOLOGY GROUP CO., LTD.,CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
- Current Assignee: BOE TECHNOLOGY GROUP CO., LTD.,CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
- Current Assignee Address: CN Beijing CN Chengdu, Sichuan
- Agency: Ladas & Parry LLP
- Priority: CN201510346651 20150619
- International Application: PCT/CN2015/094583 WO 20151113
- International Announcement: WO2016/201874 WO 20161222
- Main IPC: G02F1/1339
- IPC: G02F1/1339 ; G02F1/1343 ; G02F1/1362 ; G02F1/1333 ; G02F1/1368

Abstract:
An array substrate and a fabrication method thereof and a display device are provided. The array substrate comprises: a base substrate; a plurality of gate lines and a plurality of data lines formed on the base substrate, the plurality of gate lines and the plurality of data lines intersecting with each other to define a plurality of sub-pixels, each of the sub-pixels including a thin film transistor and a pixel electrode, and the plurality of sub-pixels including a first sub-pixel; a passivation layer formed on the base substrate and covering the gate lines, the data lines and the thin film transistor, a via hole being provided in the passivation layer and the pixel electrode being formed on the passivation layer and connected with a drain electrode or a source electrode of the thin film transistor through the via hole in each of the sub-pixels; and a first spacer, provided in the via hole of the first sub-pixel.
Public/Granted literature
- US20170146844A1 ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF, AND DISPLAY DEVICE Public/Granted day:2017-05-25
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