An array substrate provided by embodiments of the present disclosure includes a base substrate; a gate line pattern and a data line pattern formed on the base substrate; a gate insulating layer pattern formed between the gate line pattern and the data line pattern; and a spare line pattern formed on a same layer as the gate line pattern. The spare line pattern includes multiple spare lines which are substantially in parallel with the gate lines in the gate line pattern. Respective spare lines may be arranged at multiple rows of pixels defined by the gate line pattern and the data line pattern. And the respective spare lines and respective data lines in the data line pattern may have respective vertically overlapped regions.