A system configured to allow one or more timing processes to accurately keep track of one or more timers while a processor executing the one or more timing processes is in a low-power operational mode. The system is configured to set a real-time clock alarm expiration time equal to a closest expiration time, from a current time, of the one or more timers. Accordingly, upon expiration of the real-time clock alarm, an interrupt is communicated to the processor, resulting in the processor being brought out of a low-power operational mode, and executing one or more processes associated with the corresponding expired timer.