A system on chip is provided. The system on chip includes a delay control circuit configured to generate delayed clock signals having different delays, based on each of a first rising edge and a first falling edge of an input clock signal, and generate delayed data signals having different delays, based on each of a second rising edge and a second falling edge of an input data signal. The system on chip further includes a de-skew control circuit configured to control the delay control circuit to adjust a delay of each of the first rising edge, the first falling edge, the second rising edge, and the second falling edge.