- Patent Title: Method for optimizing memory access in a microprocessor including several logic cores upon resumption of executing an application, and computer implementing such a method
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Application No.: US13581279Application Date: 2011-07-07
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Publication No.: US10025633B2Publication Date: 2018-07-17
- Inventor: Philippe Couvee , Yann Kalemkarian , Benoit Welterlen
- Applicant: Philippe Couvee , Yann Kalemkarian , Benoit Welterlen
- Applicant Address: FR Les Clayes Sous Bois
- Assignee: BULL SAS
- Current Assignee: BULL SAS
- Current Assignee Address: FR Les Clayes Sous Bois
- Agency: Pillsbury Winthrop Shaw Pittman LLP
- Priority: FR1055681 20100712
- International Application: PCT/FR2011/051616 WO 20110707
- International Announcement: WO2012/007675 WO 20120119
- Main IPC: G06F9/50
- IPC: G06F9/50 ; G06F9/30 ; G06F9/46 ; G06F12/0862 ; G06F12/0806 ; G06F8/41 ; G06F12/0842

Abstract:
The invention relates in particular to optimizing memory access in a microprocessor including several logic cores upon the resumption of executing a main application, and enabling the simultaneous execution of at least two processes in an environment including a hierarchically organized shared memory including a top portion and a bottom portion, a datum being copied from the bottom portion to the top portion for processing by the application. The computer is adapted to interrupt the execution of the main application. Upon an interruption in the execution of said application, a reference to a datum stored in a top portion of the memory is stored, wherein said datum must be used in order to enable the execution of the application. After programming a resumption of the execution of the application and before the resumption thereof, said datum is accessed in a bottom portion of the memory in accordance with the reference to be stored in a top portion of the memory.
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