Invention Grant
- Patent Title: Redundancy for cache coherence systems
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Application No.: US15387625Application Date: 2016-12-21
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Publication No.: US10025677B2Publication Date: 2018-07-17
- Inventor: Benoit de Lescure , Jean Philippe Loison , Alexis Boutiller
- Applicant: Arteris, Inc.
- Applicant Address: US CA Campbell
- Assignee: ARTERIS, Inc.
- Current Assignee: ARTERIS, Inc.
- Current Assignee Address: US CA Campbell
- Main IPC: G06F7/02
- IPC: G06F7/02 ; H03M13/00 ; G06F11/16 ; G06F12/0837

Abstract:
A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.
Public/Granted literature
- US20180173597A1 REDUNDANCY FOR CACHE COHERENCE SYSTEMS Public/Granted day:2018-06-21
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