Invention Grant
- Patent Title: Cache memory system and processor system
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Application No.: US15243196Application Date: 2016-08-22
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Publication No.: US10025719B2Publication Date: 2018-07-17
- Inventor: Susumu Takeda , Shinobu Fujita
- Applicant: KABUSHIKI KAISHA TOSHIBA
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2014-033187 20140224
- Main IPC: G06F12/0895
- IPC: G06F12/0895 ; G06F12/0897 ; G06F12/1027 ; G06F12/1009 ; G06F12/1045

Abstract:
A cache memory system includes cache memories of at least one layer, at least one of the cache memories having a data cache to store data and a tag to store an address of data stored in the data cache, and a first address conversion information storage to store entry information that includes address conversion information for virtual addresses issued by a processor to physical addresses and cache presence information that indicates whether data corresponding to the converted physical address is stored in a specific cache memory of at least one layer among the cache memories.
Public/Granted literature
- US20160357683A1 CACHE MEMORY SYSTEM AND PROCESSOR SYSTEM Public/Granted day:2016-12-08
Information query
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