- Patent Title: Efficient translation reloads for page faults with host accelerator directly accessing process address space without setting up DMA with driver and kernel by process inheriting hardware context from the host accelerator
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Application No.: US14925646Application Date: 2015-10-28
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Publication No.: US10025722B2Publication Date: 2018-07-17
- Inventor: Vishal C. Aslot , Arnold Flores , Mark D. Rogers
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Patterson + Sheridan, LLP
- Main IPC: G06F12/10
- IPC: G06F12/10 ; G06F12/12 ; G06F12/1009 ; G06F12/126 ; G06F12/1027

Abstract:
Systems and computer program products to perform an operation comprising identifying, in a software page frame table by an operating system interrupt handler, a physical address of a memory page, wherein the physical address of the memory page is identified based on a virtual segment identifier (VSID) and a page number, wherein the VSID is specified in an interrupt received from a coherent accelerator and wherein the coherent accelerator generated the interrupt in response to a page fault associated with the memory page, and creating, by the operating system interrupt handler, a page table entry in a hardware page table associating the VSID and the page number with the physical address of the memory page, wherein creating the page table entry resolves the page fault.
Public/Granted literature
- US20170123999A1 EFFICIENT TRANSLATION RELOADS FOR PAGE FAULTS Public/Granted day:2017-05-04
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