Invention Grant
- Patent Title: Method and memory controller
-
Application No.: US15201723Application Date: 2016-07-05
-
Publication No.: US10026502B2Publication Date: 2018-07-17
- Inventor: Michitaka Hashimoto
- Applicant: FUJITSU LIMITED
- Applicant Address: JP Kawasaki
- Assignee: FUJITSU LIMITED
- Current Assignee: FUJITSU LIMITED
- Current Assignee Address: JP Kawasaki
- Agency: Fujitsu Patent Center
- Priority: JP2015-161817 20150819
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G11C29/38 ; G11C29/44 ; G11C29/02 ; G11C29/12 ; G11C29/50 ; G11C29/36 ; G11C11/401

Abstract:
A method includes setting a first logical value in a control register provided in a variable delay control circuit that is included in a memory controller, detecting a first stuck-at fault of a second logical value that is a value except for the first logical value, the first stuck-at fault having occurred in one of a plurality of control lines, in accordance with a result of a comparison between a logical value output from the memory controller and an expected value of the logical value, setting the second logical value in the memory controller, and detecting a second stuck-at fault of the first logical value, the second stuck-at fault having occurred in one of the plurality of control lines, in accordance with a result of a comparison between a logical value output from the memory controller and an expected value of the logical value.
Public/Granted literature
- US20170053713A1 METHOD AND MEMORY CONTROLLER Public/Granted day:2017-02-23
Information query