Invention Grant
- Patent Title: Semiconductor package and fabrication method thereof
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Application No.: US15725723Application Date: 2017-10-05
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Publication No.: US10026680B2Publication Date: 2018-07-17
- Inventor: Shing-Yih Shih
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- Main IPC: H01L21/304
- IPC: H01L21/304 ; H01L21/56 ; H01L21/58 ; H01L21/78 ; H01L23/498 ; H01L21/52 ; H01L21/48 ; H01L23/00 ; H01L23/31

Abstract:
A semiconductor package includes an interconnect component surrounded by a molding compound. The interconnect component comprises a first RDL structure. A second RDL structure is disposed on the interconnect component. A plurality of first connecting elements is disposed on the second RDL structure. A polish stop layer covers a surface of the interconnect component. A plurality of second connecting elements is disposed on and in the polish stop layer. At least one semiconductor die is mounted on the second connecting elements.
Public/Granted literature
- US20180053708A1 SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF Public/Granted day:2018-02-22
Information query
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