Invention Grant
- Patent Title: Integrated circuit chip and integrated circuit wafer with guard ring
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Application No.: US15442207Application Date: 2017-02-24
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Publication No.: US10026699B2Publication Date: 2018-07-17
- Inventor: Atsushi Obuchi , Takashi Yoneoka , Hiroshi Kaga
- Applicant: Synaptics Japan GK
- Applicant Address: JP Tokyo
- Assignee: Synaptics Japan GK
- Current Assignee: Synaptics Japan GK
- Current Assignee Address: JP Tokyo
- Agency: Patterson + Sheridan, LLP
- Priority: JP2016-059397 20160324
- Main IPC: H01L23/552
- IPC: H01L23/552 ; H01L23/58 ; H01L21/78 ; H01L21/66 ; H01L23/482 ; H01L23/485 ; H01L23/00

Abstract:
A large scale integrated circuit chip includes a semiconductor circuit having a multilayered wiring structure, a metal guard ring surrounding the semiconductor circuit, and a plurality of external connection terminals, on a semiconductor circuit. The plurality of external connection terminals connect to an uppermost-layer wiring of the multilayered wiring structure and are exposed on a surface of the large scale integrated circuit chip. A predetermined external connection terminal conducts to a predetermined wiring through a conductive via within the guard ring and conducts to a conductive piece through another conductive via outside the guard ring. One side of the external connection terminal extending over the guard ring connects to the conductive piece, and the other side of the external connection terminal connects to the uppermost-layer wiring within the guard ring. Thus, a cutout part is not necessary in the guard ring.
Public/Granted literature
- US20170278805A1 LARGE SCALE INTEGRATED CIRCUIT CHIP AND LARGE SCALE INTEGRATED CIRCUIT WAFER Public/Granted day:2017-09-28
Information query
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