- Patent Title: Single mask level including a resistor and a through-gate implant
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Application No.: US15669246Application Date: 2017-08-04
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Publication No.: US10026730B2Publication Date: 2018-07-17
- Inventor: Mahalingam Nandakumar , Douglas Tad Grider, III
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/94 ; H01L31/062 ; H01L31/113 ; H01L31/119 ; H01L27/06 ; H01L29/732 ; H01L27/092 ; H01L49/02 ; H01L29/06 ; H01L29/66 ; H01L29/167 ; H01L29/08 ; H01L29/10 ; H01L21/8238 ; H01L21/266 ; H01L21/265 ; H01L21/3215 ; H01L21/28 ; H01L21/8249

Abstract:
A method of forming an IC includes providing a field dielectric in a portion of a semiconductor surface, a bipolar or Schottky diode (BSD) class device area, a CMOS transistor area, and a resistor area. A polysilicon layer is deposited to provide a polysilicon gate area for MOS transistors in the CMOS transistor area, over the BSD class device area, and over the field dielectric for providing a polysilicon resistor in the resistor area. A first mask pattern is formed on the polysilicon layer. Using the first mask pattern, first implanting (I1) of the polysilicon resistor providing a first projected range (RP1) RP1. I2 provides a CMOS implant into the semiconductor surface layer in the CMOS transistor area and/or a BSD implant into the semiconductor surface layer in the BSD area.
Public/Granted literature
- US20170338223A1 SINGLE MASK LEVEL INCLUDING A RESISTOR AND A THROUGH-GATE IMPLANT Public/Granted day:2017-11-23
Information query
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