The present disclosure presents a method of manufacturing a semiconductor structure, in which a memory cell is formed on a semiconductor substrate, the memory cell including a control gate, a select gate and a source region. A logic device is formed on the semiconductor substrate, where the logic device includes a gate layer and a source/drain region. The select gate is thinned such that the select gate is lower than an upper surface of the control gate. A silicidation operation is performed for the source region and the select gate of the memory cell, and a dielectric layer is deposited over the source region and the drain region of the memory cell, and the drain/source region of the logic device.