Invention Grant
- Patent Title: Stacked type semiconductor memory device and method for manufacturing same
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Application No.: US15255913Application Date: 2016-09-02
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Publication No.: US10026748B2Publication Date: 2018-07-17
- Inventor: Hiroshi Nakaki
- Applicant: TOSHIBA MEMORY CORPORATION
- Applicant Address: JP Minato-ku
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C16/04 ; H01L27/115 ; H01L29/792 ; H01L29/51 ; H01L29/423 ; H01L29/66 ; H01L29/788 ; H01L27/11582 ; H01L27/11565

Abstract:
According to the embodiment, the semiconductor device includes: a stacked body; first interconnect and a second interconnect; a first columnar portion, a second columnar portion, a third columnar portion, and a fourth columnar portion; a first intermediate interconnect; a first connection portion; a second connection portion; and a second intermediate interconnect. The stacked body includes a plurality of electrode layers. The first interconnect and the second interconnect are provided on the stacked body, and extend in a first direction crossing a stacking direction of the stacked body. The first intermediate interconnect is electrically connected to the first interconnect, the first columnar portion, and the second columnar portion. The second intermediate interconnect is provided at a height different from a height of the first intermediate interconnect, and is electrically connected to the second interconnect, the third columnar portion, and the fourth columnar portion.
Public/Granted literature
- US20170263628A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME Public/Granted day:2017-09-14
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