Invention Grant
- Patent Title: Embedded SiGe process for multi-threshold PMOS transistors
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Application No.: US14845112Application Date: 2015-09-03
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Publication No.: US10026837B2Publication Date: 2018-07-17
- Inventor: Younsung Choi , Deborah J. Riley
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L29/08 ; H01L29/161 ; H01L27/088 ; H01L21/8234 ; H01L29/165
Abstract:
An integrated circuit and method having a first PMOS transistor with extension and pocket implants and with SiGe source and drains and having a second PMOS transistor without extension and without pocket implants and with SiGe source and drains. The distance from the SiGe source and drains to the gate of the first PMOS transistor is greater than the distance from the SiGe source and drains to the gate of the second PMOS transistor and the turn on voltage of the first PMOS transistor is at least 50 mV higher than the turn on voltage of the second PMOS transistor.
Public/Granted literature
- US20170069755A1 EMBEDDED SIGE PROCESS FOR MULTI-THRESHOLD PMOS TRANSISTORS Public/Granted day:2017-03-09
Information query
IPC分类:
