Invention Grant
- Patent Title: Maximizing cubic phase group III-nitride on patterned silicon
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Application No.: US15490528Application Date: 2017-04-18
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Publication No.: US10027086B2Publication Date: 2018-07-17
- Inventor: Can Bayram , Richard Liu
- Applicant: The Board of Trustees of the University of Illinois
- Applicant Address: US IL Urbana
- Assignee: Board of Trustees of the University of Illinois
- Current Assignee: Board of Trustees of the University of Illinois
- Current Assignee Address: US IL Urbana
- Agency: Lowenstein Sandler LLP
- Main IPC: H01S5/00
- IPC: H01S5/00 ; H01S5/02 ; H01S5/323 ; H01S5/30 ; H01L29/20 ; H01L31/0304 ; H01L33/32

Abstract:
A device including a non-polarization material includes a number of layers. A first layer of silicon (100) defines a U-shaped groove having a bottom portion (100) and silicon sidewalls (111) at an angle to the bottom portion (100). A second layer of a patterned dielectric on top of the silicon (100) defines vertical sidewalls of the U-shaped groove. A third layer of a buffer covers the first layer and the second layer. A fourth layer of gallium nitride is deposited on the buffer within the U-shaped groove, the fourth layer including cubic gallium nitride (c-GaN) formed at merged growth fronts of hexagonal gallium nitride (h-GaN) that extend from the silicon sidewalls (111), wherein a deposition thickness (h) of the gallium nitride above the first layer of silicon (100) is such that the c-GaN completely covers the h-GaN between the vertical sidewalls.
Public/Granted literature
- US20170310076A1 MAXIMIZING CUBIC PHASE GROUP III-NITRIDE ON PATTERNED SILICON Public/Granted day:2017-10-26
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