- Patent Title: Semiconductor integrated circuit that stops power supply to at least a storage area of a first SRAM in a power-saving mode, and control method of semiconductor integrated circuit
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Application No.: US15381300Application Date: 2016-12-16
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Publication No.: US10027906B2Publication Date: 2018-07-17
- Inventor: Hiroaki Niitsuma
- Applicant: CANON KABUSHIKI KAISHA
- Applicant Address: JP Tokyo
- Assignee: Canon Kabushiki Kaisha
- Current Assignee: Canon Kabushiki Kaisha
- Current Assignee Address: JP Tokyo
- Agency: Fitzpatrick, Cella, Harper & Scinto
- Priority: JP2016-001754 20160107
- Main IPC: H04N5/225
- IPC: H04N5/225 ; H04N5/335 ; H04N5/369 ; H04N1/00

Abstract:
The image forming apparatus of the present invention is a semiconductor integrated circuit including: a first image processing module; a second image processing module; a first SRAM configured to temporarily store image data for which the first image processing has been performed by the first image processing module; a second SRAM configured to store a parameter for performing the second image processing for image data that is input to the second image processing module; and a control unit. The control unit stops power supply to the first SRAM, continues to supply power to a storage area of the second SRAM in which the parameter is stored, and stops power supply to a control area for writing data to the storage area of the second SRAM based on that a condition to cause the semiconductor integrated circuit to make a transition into a power-saving mode is satisfied.
Public/Granted literature
- US20170201697A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT Public/Granted day:2017-07-13
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