When a MISFET is formed by using a gate last process and replacing dummy gate electrodes with metal gate electrodes, both of respective cap insulating films and an interlayer insulating film over a control gate electrode and the dummy gate electrodes are polished to prevent excessive polishing of the upper surface of the interlayer insulating film and the occurrence of dishing. In the gate last process, the interlayer insulating film is formed to cover the control gate electrode and the dummy gate electrodes as well as the cap insulating films located thereover. After the upper surface of the interlayer insulating is polished to expose the cap insulating films from the interlayer insulating films, etching is performed to selectively remove the cap insulating films. Subsequently, the upper surfaces of the interlayer insulating films are polished.