- Patent Title: Apparatus and methods for generating a selection signal to perform an arbitration in a single cycle between multiple signal inputs having respective data to send
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Application No.: US15367218Application Date: 2016-12-02
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Publication No.: US10037295B2Publication Date: 2018-07-31
- Inventor: Supreet Jeloka , Sandunmalee Nilmini Abeyratne , Ronald George Dreslinski , Reetuparna Das , Trevor Nigel Mudge , David Theodore Blaauw
- Applicant: The Regents of the University of Michigan
- Applicant Address: US MI Ann Arbor
- Assignee: The Regents of the University of Michigan
- Current Assignee: The Regents of the University of Michigan
- Current Assignee Address: US MI Ann Arbor
- Agency: Nixon & Vanderhye P.C.
- Main IPC: G06F13/00
- IPC: G06F13/00 ; G06F13/40 ; G06F13/374 ; G11C7/10 ; H03K17/693 ; G06F13/16

Abstract:
An interconnect within an integrated circuit provides arbitration to select one of a plurality of signal inputs for connection to a signal output. The arbitration applied uses a first arbitration parameter value, in the form of a time stamp value, and, if two or more signal inputs share such a time stamp value, then uses a second arbitration parameter, in the form of a least recently granted value. The time increment applied to the time stamp value associated with each signal input when it is granted access to the signal output is selected to reflect the quality of service to be associated with that signal input. When a comparison is made between time stamp values, the lowest time stamp value is given priority. A large time increment value corresponds to a low priority (quality of service).
Public/Granted literature
- US20170083471A1 SINGLE CYCLE ARBITRATION Public/Granted day:2017-03-23
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